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Day 1: Welcome to Hardware Thinking

Week 1 · Session 1 of 16

Pre-Class Video Segments

Segment 1: HDL ≠ Software

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Segment 2: Synthesis vs. Simulation

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Segment 3: Anatomy of a Verilog Module

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Segment 4: Digital Logic Refresher

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Lecture Code Examples

Code shown during the pre-class video. Use these as reference when working on the lab exercises.