Barcelona Schedule
Summer 2026 — HDL for Digital System Design Abroad
This page shows the Barcelona-adapted course calendar. The baseline
16-day curriculum maps onto 14 teaching sessions plus academic visits
and a guest lecture.
For the full adaptation plan, see the
Barcelona Adaptation Document.
Calendar Overview
Week 1: Verilog Foundations (May 25–29)
| Date |
Type |
Session |
| Mon 5/25 |
Class |
D1: Welcome to Hardware Thinking |
| Tue 5/26 |
Class |
D2: Data Types, Vectors & Operators |
| Wed 5/27 |
Class |
D3: Combinational Logic · PM: Sagrada Familia |
| Thu 5/28 |
Excursion |
Montserrat Day Trip |
| Fri 5/29 |
Class |
D4: Clocked Logic & RTL Thinking |
Week 2: Sequential Design & Verification (Jun 1–5)
| Date |
Type |
Session |
| Mon 6/1 |
Merged |
D5+D6: Counters, Testbenches & AI Verif · PM: Semidynamics |
| Tue 6/2 |
Class |
D7: FSMs · PM: HP Barcelona |
| Wed 6/3 |
Class |
D8: Hierarchy & Parameters · Eve: Cooking |
| Thu 6/4 |
Class |
D9: Memory Systems |
| Fri 6/5 |
Free |
Independent study / explore Barcelona |
Week 3: Timing, UART & SystemVerilog (Jun 8–12)
| Date |
Type |
Session |
| Mon 6/8 |
Class |
D10: Timing & Numerical Architectures |
| Tue 6/9 |
Condensed |
D11: UART TX (RX = stretch) · Eve: Flamenco |
| Wed 6/10 |
Class |
D12: SV for Design · PM: Park Güell |
| Thu 6/11 |
Class |
D13: SV for Verification |
| Fri 6/12 |
Free |
Independent project work |
Week 4: Integration & Demonstration (Jun 15–19)
| Date |
Type |
Session |
| Mon 6/15 |
Visit |
Barcelona Metro Control Room |
| Tue 6/16 |
Class |
D14: Project Build Day |
| Wed 6/17 |
Guest |
RISC-V Lecture — David Castells Rufas |
| Thu 6/18 |
Class |
D15: Demos & Course Wrap |
| Fri 6/19 |
Free |
Departure / free day |
Key Dates
- Project selection: Thu 6/4
- Core module due: Thu 6/11
- Build day: Tue 6/16
- Demo day: Thu 6/18