CRAFT Overlay — D13 — SystemVerilog for Verification¶

Date: Thu 6/11

🌍 Contextualize¶

"Assertions are executable specifications. In industry, the verification engineer writes assertions before the designer writes RTL. When the design violates a property, the assertion fires immediately — not after hours of waveform debugging."

⚠️ Reframe¶

"If You're Thinking Like a Programmer: testing is something you do at the end. Reframe: Assertions live inside your design. They fire the instant something goes wrong. They're not tests — they're contracts."

🔑 Key Insight¶

"An assertion that never fires might mean your design is correct — or it might mean your testbench never exercises that path. Coverage tells you which."

🤖 Check the Machine¶

"Prompt AI to add 5 assertions to your UART TX module. Run them. Do any fire? Then ask AI to generate stimulus that should trigger each assertion. This is constraint-based testing."

🔗 Transfer¶

"Next week: Metro visit Monday, project build Tuesday, RISC-V lecture Wednesday, demos Thursday. Your project scope is locked — start building tonight."

Back to Barcelona Day Plan Baseline D14 Materials

This overlay supplements the baseline D14 daily plan (SV Verification). All lab exercises and lecture content come from the baseline D14 materials.