CRAFT Overlay — D2 — Data Types, Vectors & Operators¶

Date: Tue 5/26

🌍 Contextualize¶

"Binary data is in everything digital around you — your phone, the metro ticket reader, the airport baggage scanner. Today you learn how HDL represents that data."

⚠️ Reframe¶

"If You're Thinking Like a Programmer: variables are storage boxes you put values into. Reframe: wire is a physical connection — it doesn't store anything. reg is a storage element, not a variable."

🔑 Key Insight¶

"In Verilog, the name reg is misleading. It doesn't mean register — it means 'the simulator needs to remember this value.' SystemVerilog fixes this with logic."

🤖 Check the Machine¶

(None — pre-AI-thread)

🔗 Transfer¶

"Tomorrow: combinational logic — making decisions in hardware with always @(*), if, and case. Plus you'll see your first synthesis output."

Back to Barcelona Day Plan Baseline D2 Materials

This overlay supplements the baseline D2 daily plan. All lab exercises and lecture content come from the baseline D2 materials.