Accelerated HDL for Digital System Design¶
UCF · College of Engineering & Computer Science · Department of ECE
A 4-week intensive course in Verilog and digital system design. Open-source toolchain, real FPGA hardware, AI-assisted verification.
16
Sessions
4 weeks × 4 days
12.2h
Video Content
56 segments
38+
Lab Exercises
Hands-on every day
iCE40
FPGA Platform
Nandland Go Board
Cross-Cutting Threads¶
AI-Assisted Verification
D6 → D8 → D12 → D14 → D16
PPA Analysis
D3 → D8 → D10 → D12 → D14
Constraint-Based Design
D3 → D7 → D8 → D10 → D14
AI Tool Literacy
D6 → D12 → D14 → D16
Weekly Arc¶
1
Verilog Foundations & Combinational Design
2
Sequential Design, Verification & AI Testing
3
Memory, Communication & Numerical Architectures
4
Advanced Design, Verification & Final Project
What Makes This Course Different¶
Hands-on from Day 1
Real hardware, real toolchain, every session.
AI-Assisted Verification
Learn to prompt, evaluate, and correct AI-generated testbenches.
PPA Awareness
Resource analysis via yosys stat becomes a habit, not a one-off exercise.
Open-Source Everything
No license servers, no vendor lock-in — you keep the tools forever.
Toolchain Quick Reference¶
# Simulation (Icarus Verilog + GTKWave)
iverilog -o sim.vvp -g2012 tb_module.v module.v
vvp sim.vvp
gtkwave dump.vcd
# Synthesis & Programming (iCE40 open-source flow)
yosys -p "synth_ice40 -top top_module -json top.json" top.v
nextpnr-ice40 --hx1k --package vq100 --pcf go_board.pcf --json top.json --asc top.asc
icepack top.asc top.bin
iceprog top.bin