Guest Lecture: RISC-V — David Castells Rufas¶
Date: Wednesday, June 17 · 10:00 AM Location: IL3 classroom Speaker: David Castells Rufas, Dept. of Microelectronics and Electronic Systems, Universitat Autònoma de Barcelona
About the Speaker¶
David is a RISC-V expert in the Department of Microelectronics and Electronic Systems at UAB. His research focuses on RISC-V applications and implementations.
Pre-Lecture Prep (assigned end of Tue 6/16 class)¶
🌍 Connection to course: "David designs RISC-V processors in the same HDL you've been writing for four weeks. This lecture is where your skills connect to processor architecture."
Come with 2 prepared questions about how course concepts apply to processor design. Examples: - "How do you use parameterized modules in your RISC-V cores?" - "What does your verification flow look like?" - "How do you make area/performance trade-offs?"
During the Lecture¶
Note connections to course concepts as you listen:
- FSMs — pipeline control, instruction decode
- Parameterization — configurable cores
- Memory — register file, caches
- Timing — pipeline stages, clock frequency
- Verification — how they test
Role in CRAFT Arc¶
This is the course's capstone 🌍 Contextualize + 🔗 Transfer
moment. "You now have the foundation to understand and contribute
to what David does. The path from your first hello_led module to
a RISC-V core is a matter of scale, not fundamentally different
skills."