Day 1 · Welcome to Hardware Thinking

Digital Logic Refresher

Video 4 of 4 · ~8 minutes

Dr. Mike Borowczak · Electrical & Computer Engineering · CECS · UCF

🌍 Where This Lives

Why Refresh?

You saw gates in a prior class. This refresher is calibration: we're making sure we use the same names, truth tables, and symbols for the rest of the course. If we say “priority encoder” in Week 2 and half the class hears something different, debugging becomes impossible.

What's Different This Time

Now we're looking at gates through the lens of “what Verilog builds.” The & operator is an AND gate. The ternary ?: is a mux. Every construct in the rest of the course will map back to the primitives in this video.

What You Must Have Cold

Logic gates: AND, OR, NOT, NAND, NOR, XOR, XNOR

Boolean algebra: DeMorgan's, distribution, complement

Combinational vs. sequential:
Combinational = f(current inputs)
Sequential = f(inputs, stored state)

Truth tables ↔ Boolean expressions: both directions

The D flip-flop: captures D on clock edge

Gates → Verilog: The Translation Table

Digital Logic	Verilog
Wire	`assign y = a;`
AND gate	`assign y = a & b;`
OR gate	`assign y = a \| b;`
NOT (inverter)	`assign y = ~a;`
XOR gate	`assign y = a ^ b;`
2:1 Multiplexer	`assign y = sel ? a : b;`
D flip-flop	`always @(posedge clk) q <= d;`

Compound Expressions

// NAND: ~(a & b)    NOR: ~(a | b)

// Sum-of-products: y = AB + CD
assign y = (a & b) | (c & d);

// DeMorgan's: these produce IDENTICAL hardware
assign y1 = ~(a & b);
assign y2 = ~a | ~b;     // same gate!

The synthesizer optimizes. Write for readability — the tool reduces to minimum hardware.

▶ LIVE DEMO

Gates in Verilog

Gate-level Verilog → assign equivalents

AND → OR → XOR → compound expression → verify identical output

Combinational vs. Sequential in Verilog

Combinational

// Output changes whenever
// inputs change
assign y = a & b;

No clock. No memory. Weeks 1–2 focus.

Sequential

// Output changes only on
// the clock edge
always @(posedge clk)
    q <= d;

Clock-driven. Has memory. Introduced Day 4.

You Already Know the Hardware

Gates ✓ Boolean algebra ✓ Truth tables ✓ Flip-flops ✓

This course teaches you the language to describe it.

🤖 Check the Machine

Ask an AI assistant: “Given a 3-input multiplexer truth table, write the minimal Verilog using assign and the conditional operator. Then tell me how many LUT4s it will take on an iCE40.”

TASK

Mux design from truth table + predict LUT count.

BEFORE

Predict: 3-input mux has 3 data + 2 select = 5 inputs. Doesn't fit 1 LUT4. So 2+.

AFTER

Verify with: yosys -p "read_verilog mux.v; synth_ice40; stat".

TAKEAWAY

AI can write correct Verilog. AI cannot always predict exact LUT count. Tool wins.

Pre-Class Self-Check

Pause the video and try each question before revealing the answer.

Q1: Name three fundamental differences between writing software and writing Verilog.

① Execution model: sequential vs. concurrent. ② Resources: more code = more time (SW) vs. more hardware (HW). ③ No dynamic allocation: hardware is fixed at synthesis time.

Pre-Class Self-Check (cont.)

Q2: What happens to #10 during synthesis? During simulation?

Simulation: waits 10 time units. Synthesis: completely ignored. This is why you never use #delay in synthesizable code.

Q3: Write a complete Verilog module that connects i_switch to o_led.

module led_driver (
    input  wire i_switch,
    output wire o_led
);
    assign o_led = i_switch;
endmodule

Pre-Class Self-Check (cont.)

Q4: What does assign mean — a one-time computation or something else?

A permanent physical wire connection. Not one-time. The output continuously reflects the input — like a wire soldered between two points.

Q5: Does the order of these assign statements matter?

assign y2 = a | b;
assign y1 = a & b;

No. Both create hardware that exists simultaneously. Swapping them produces identical hardware. This is different from software.

If Q3 felt hard, re-watch Video 3. Getting the module template into muscle memory saves you time in lab.

🔗 End of Day 1

Tomorrow: Data Types & Operators

Day 2 · Combinational Building Blocks

▸ WHY THIS MATTERS NEXT

You now have the mental model: Verilog describes concurrent hardware, two tools consume it (synthesis vs simulation), and modules are chips with named pins. Day 2 gives you the working vocabulary — how to declare signals and combine them. By end of Day 2 you'll decode a hex digit to a 7-segment display on the Go Board. Real hardware. Real output. Tomorrow.