Day 13 Lab: SystemVerilog for Design¶
Starter Code & Notebooks
Download All Starter Code (.zip)
Open in JupyterLab Download .ipynb View on GitHub
Individual exercise downloads and file links are below each exercise.
Overview¶
Refactor existing Verilog modules into SystemVerilog using logic,
always_ff, always_comb, enum, and struct. Compare behavior
and synthesis results.
Prerequisites¶
- Pre-class video on SystemVerilog design constructs
- Working ALU, traffic light FSM, and UART TX from prior labs
Toolchain Notes¶
- Simulation:
iverilog -g2012(limited SV support) - Synthesis:
yosys read_verilog -sv - Linting:
verilator --lint-only -Wall(if installed)
Exercises¶
| # | Exercise | Time | Key SLOs |
|---|---|---|---|
| 1 | ALU Refactor | 25 min | 13.1, 13.2, 13.6 |
| 2 | FSM Refactor | 25 min | 13.2, 13.3, 13.6 |
| 3 | UART TX Refactor | 30 min | 13.1–13.4 |
| 4 | Final Project Design | 30 min | — |
| 5 | Package (Stretch) | 15 min | 13.5 |
Deliverables¶
- SV-refactored ALU passing all original tests
- SV-refactored FSM with enum states and .name() debug output
- SV-refactored UART TX with struct-based signal grouping
- Final project block diagram and module inventory