CRAFT Overlay — D5+D6 — Counters, Testbenches & AI Verification¶

Date: Mon 6/1

🌍 Contextualize¶

"Every digital system counts, shifts, and debounces. The processor pipelines at Semidynamics — the company you'll visit this afternoon — are built from the same counters and shift registers you're about to design."

⚠️ Reframe¶

"If You're Thinking Like a Programmer: delay() handles timing, and if it simulates it works. Reframe: Mechanical contacts bounce for milliseconds — you need a saturating counter, not a delay(). And simulation proves correctness only for tested cases. It cannot prove the absence of bugs."

🔑 Key Insight¶

"A testbench is not optional — it's how you know your design works. Writing it after the design is common; writing it before is better."

🤖 Check the Machine¶

"Prompt AI to generate a testbench for your debounce module. Does it handle bounce timing? Reset? Compare its coverage against your manual TB — which found more bugs?"

🔗 Transfer¶

"You can now build sequential circuits AND verify them — both manually and with AI assistance. Tomorrow: Finite State Machines — the design pattern that ties everything together."

Visit/Activity Connection¶

PM: Semidynamics — Ask about verification: how much of their RISC-V development time is verification? What role does AI play in their test workflows?

Back to Barcelona Day Plan Baseline D5 Materials Baseline D6 Materials

This overlay supplements the baseline daily plan. All lab exercises and lecture content come from the baseline D5 + D6 materials.