HDL for Digital System Design — Barcelona Abroad¶
UCF Study Abroad · Barcelona, Spain · Summer 2026
The full 16-day HDL curriculum, adapted for a study-abroad format: 14 teaching sessions, 3 academic visits, a guest RISC-V lecture, and the CRAFT pedagogical overlay woven into every session.
Weekly Arc¶
Academic Visits & Enrichment¶
RISC-V vector processor startup — see how RTL meets commercial silicon design in a Barcelona fab-adjacent company.
Large-scale hardware verification and test infrastructure at a major semiconductor site.
Real-time embedded systems managing a city's transit network — digital design in critical infrastructure.
David Castells Rufas on open-source ISA design — connecting course HDL skills to the RISC-V ecosystem.
Course Grading¶
Labs & Technical Work (85%)
| Component | Weight |
|---|---|
| Lab exercises (12 sessions) | 72% |
| Final project | 5% |
| AI workflow portfolio | 8% |
Activities & Engagement (15%)
| Component | Weight |
|---|---|
| Visit reflections (3 write-ups) | 10% |
| Participation & engagement | 5% |
See the Barcelona Project Spec for project-specific deliverables and rubric.
What Makes the Abroad Edition Different¶
Contextualize → Reframe → Assemble → Fortify → Transfer. Each 2.5-hour session follows this research-backed cycle.
Academic visits replace textbook motivation — you see HDL concepts in production before you build them in lab.
14 teaching sessions cover the full 16-day curriculum. Two strategic merges, zero cut corners.
No license servers, no vendor lock-in — the same iCE40 toolchain travels with you.