Anatomy of a Verilog Module

The Module: Verilog's Building Block

Every Verilog design is composed of modules.

⚠️ If You're Thinking Like a Programmer…

The Module Template

module led_driver (
    input  wire i_switch,
    output wire o_led
);

    assign o_led = i_switch;

endmodule

Port Style: ANSI (Modern) vs. Non-ANSI

module adder (
    input  wire [3:0] i_a,
    input  wire [3:0] i_b,
    output wire [4:0] o_sum
);
    assign o_sum = i_a + i_b;
endmodule

module adder (i_a, i_b, o_sum);
    input  [3:0] i_a;
    input  [3:0] i_b;
    output [4:0] o_sum;

    assign o_sum = i_a + i_b;
endmodule

Naming Conventions

module my_design (
    input  wire       i_clk,        // i_ = input
    input  wire       i_reset,
    input  wire [7:0] i_data,
    output wire       o_valid,       // o_ = output
    output reg  [7:0] o_result
);
    wire [7:0] w_intermediate;       // w_ = internal wire
    reg  [3:0] r_counter;            // r_ = register (sequential)
    // ...

Common Error #1: The Missing Semicolon

module my_module (
    input  wire a,
    output wire y
)                         // ← MISSING SEMICOLON
    assign y = a;
endmodule

module my_module (
    input  wire a,
    output wire y
);                        // ← CORRECT
    assign y = a;
endmodule

You will make this mistake. The error message won't point to the right line. Now you know what to look for.

Common Error #2: Mismatched Widths

module oops (
    input  wire [7:0] i_data,    // 8 bits
    output wire [3:0] o_result   // 4 bits
);
    assign o_result = i_data;    // ← truncation! upper 4 bits lost
endmodule

🤖 Check the Machine

Ask an AI assistant: “What happens if I declare a signal as output reg but then drive it with an assign statement outside the module?”

Key Takeaways