Video 4 of 4 · ~10 minutes
Dr. Mike Borowczak · Electrical & Computer Engineering · CECS · UCF
Coverage is how verification teams answer the tape-out question: “are we done?” Tier-1 chip companies hold tape-out readiness reviews where coverage closure is a gating metric — 100% code coverage, 98%+ functional coverage, all cover points hit. No coverage closure, no tape-out. The DV engineer's semester ends at 100% on the coverage dashboard.
Your testbenches have been measured by “does it pass?” Today asks the harder question: “have I exercised every state and transition?” Plus we take a final look at the landscape — formal, UVM, HLS, open silicon — and what a hardware career looks like in 2026 and beyond.
“My testbench has 50 test cases. All 50 pass. The design works.”
50 passing tests say 50 scenarios work. They say nothing about the other scenarios you didn't write. The FSM might have 12 states and only 7 got exercised. Lines 42-56 of your RTL might never have been executed in any test. That untested code could contain anything — bugs, paths to unexpected states, dead code. Coverage measures what you actually touched.
| Type | Measures | Tool gives it to you |
|---|---|---|
| Code coverage | Which lines / branches / toggles / FSM transitions were executed | Automatic — simulator instruments the RTL |
| Functional coverage | Which scenarios you care about were exercised (e.g., “FIFO full while RX active”) | You declare cover points; tool counts |
// Declare scenarios you care about
covergroup uart_cg @(posedge clk);
// Did we see each FSM state?
state_cov: coverpoint r_state {
bins idle = {TX_IDLE};
bins start = {TX_START};
bins data = {TX_DATA};
bins stop = {TX_STOP};
}
// Did we transmit each byte value?
byte_cov: coverpoint i_data iff (i_valid) {
bins zero = {8'h00};
bins all_ones = {8'hFF};
bins typical = {[1:254]};
}
// Cross: which byte in which state?
state_x_byte: cross state_cov, byte_cov;
endgroup
uart_cg cov_instance = new();Your UART echo-server testbench reports:
Question: is this ready to ship, or what do you investigate first?
Formal verification — proves assertions hold for all inputs, not just simulated ones. Industry adoption is climbing as tools get cheaper (SymbiYosys on the open side; Jasper/VC Formal on commercial). Your assertion-writing skill ports directly.
UVM (Universal Verification Methodology) — the industry standard for building reusable testbench environments. Object-oriented SV. Overkill for small designs; essential for large teams.
High-Level Synthesis (HLS) — writes RTL from C/C++/SystemC. Productivity win for data-path designs (filters, vision accelerators). Growing, but RTL is not going away.
Open-source silicon — Skywater 130nm PDK, OpenROAD, OpenLane, Google's MPW shuttle program. You can now tape out your own chip for free (small area). This was impossible 5 years ago. Revolutionary for education and hobbyists.
AI-assisted design — not just verification (Day 14.2) but RTL generation, debugging, floorplanning. Still maturing; watch closely.
| Role | What they do | HDL skill matters because |
|---|---|---|
| Digital Designer | Write RTL for CPU / GPU / accelerator blocks | Obvious — this is the job |
| Design Verification (DV) | Write testbenches, assertions, cover points | Your assertions + UVM + coverage skill |
| FPGA Engineer | Embedded systems, signal processing, prototyping | Go Board / Lattice / Xilinx flow knowledge |
| Physical Designer | Place-and-route, timing closure | You read synthesis/P&R reports already |
| Hardware Security | Side-channel analysis, secure HDL patterns | CDC/timing knowledge → attack surface understanding |
| Compiler Engineer | HLS, ML accelerators, domain-specific silicon | HDL fluency to reason about compiler output |
Ask AI: “Given my UART design and testbench, suggest cover points (functional coverage) that would catch scenarios I might have missed.”
TASK
AI proposes cover points for your UART.
BEFORE
Predict: FSM state × byte value cross, reset-during-transmit, back-to-back frames, parity errors.
AFTER
Strong AI gives cross-coverage + bins. Weak AI lists flat state coverage only.
TAKEAWAY
Cross-coverage is the mark of a mature coverage plan. Look for it.
① Coverage = how you answer “are we done?” Not a feeling; a measurement.
② Code coverage = syntactic floor. Functional coverage = semantic ceiling.
③ Cross coverage is where interesting bugs live.
④ Your HDL skill opens doors to 6+ career tracks, not just “digital designer.”
Q1: Your code coverage is 100%. Can you ship?
Q2: What's the difference between state coverage and transition coverage for an FSM?
Q3: What is formal verification, in one sentence?
Q4: You know Verilog/SV and FPGA flow. Which career paths are open to you besides “RTL designer”?
🔗 End of Day 14 · Transition to Capstone
The capstone integration — your library, on silicon
▸ WHY THIS MATTERS NEXT
You now have every tool: RTL fluency, SystemVerilog, assertions, coverage, PPA discipline. Day 15 is when you use them. The briefing covers the #1 failure mode of integration projects, the incremental discipline that avoids it, common late-stage panics and their fixes, and UART printf-debugging as your primary silicon telemetry tool. Then you build.