Day 10 · Timing, Numerics & PPA

Open-Source ASIC PPA

Video 4 of 4 · ~8 minutes

Dr. Mike Borowczak · Electrical & Computer Engineering · CECS · UCF

🌍 Where This Lives

In Industry

Skywater 130 nm (open PDK) and GlobalFoundries 180 nm are real foundry processes you can tape out to via the Google/Efabless sponsorship programs — for under $10k per design. Students and researchers have shipped working silicon from their laptops. OpenROAD and OpenLane are the tool flows. What used to be a $500k EDA license barrier is now open-source. The barrier to entry for custom silicon is the lowest it has ever been.

In This Course

You won't do a full tapeout — but you'll learn to read ASIC-flow reports, understand why FPGA and ASIC PPA differ, and appreciate why the RTL discipline you've been building matters even more when silicon is permanent. This context is career-shaping: it connects your current course to real silicon careers.

⚠️ FPGA PPA Is a Proxy — Not the Final Answer

❌ Wrong Model

“My design fits in 500 LUTs and runs at 150 MHz on iCE40. That's the PPA. Moving to ASIC wouldn't change anything fundamental.”

✓ Right Model

FPGA and ASIC have different cost models. On FPGA: LUTs and EBRs are free (already on the chip) but you pay per switched gate in power. On ASIC: flops are expensive (each is fabricated silicon), combinational logic is cheap, and clock tree power dominates. The same RTL produces different-shaped hardware with different winners. FPGA numbers predict the shape of ASIC tradeoffs, not the magnitudes.

The receipt: An FPGA “good” design at 100 MHz is often a mediocre ASIC design. ASIC Fmax targets are often 500 MHz-3 GHz, so what looks fast on iCE40 barely clears the ASIC bar.

👁️ I Do — FPGA vs. ASIC PPA Side-by-Side

Metric	FPGA (iCE40 HX1K)	ASIC (Skywater 130 nm)
Area unit	LUT, DFF, EBR (abstract)	µm² of silicon (real)
Typical Fmax	100-200 MHz	500 MHz - 3 GHz
Flop cost	Free (already on chip)	Real silicon, ~50 µm² each
Power model	Fixed static + dynamic ~ f × activity	Static (leakage) + Dynamic + Clock tree
Critical path	Net routing dominates	Combinational logic dominates
Timing margins	Easy (slow clocks)	Tight — every ps matters
Memory	Fixed EBRs	Custom-sized SRAM macros
Bring-up cost	Flash and go (seconds)	6-12 months + $10k-$10M

🤝 We Do — OpenROAD / OpenLane Flow

The open-source ASIC design flow mirrors your FPGA flow, but with more steps:

  Your Verilog
      │
      ▼
  Yosys ────────────→ synthesis to gate-level
      │
      ▼
  OpenROAD ────┬─→ floorplanning
               ├─→ placement
               ├─→ clock tree synthesis (CTS)
               ├─→ routing
               └─→ timing signoff
      │
      ▼
  GDS-II layout ──→ send to foundry

Together: Same Yosys you've been using. OpenROAD takes the gate-level netlist and physically lays it out on silicon. The whole flow runs on your laptop — no licenses — and produces a GDS-II file the foundry turns into chips. OpenLane is a Make-like wrapper that automates all of this with one command.

A Concrete Comparison

Your Week 2 traffic-light FSM, run through both flows:

Metric	iCE40 HX1K	Skywater 130 nm
Area	7 cells (2 DFF + 5 LUT)	~185 µm² (8 std cells)
Fmax	162 MHz	780 MHz
Power @ 25 MHz	~2 µW (FPGA static dominates)	~0.3 µW
Power @ max Fmax	~12 µW	~15 µW

What to notice: Same RTL, 5× higher Fmax on ASIC. At low clocks, ASIC is much lower power; at max Fmax, they converge (different reasons: FPGA has configurable routing overhead; ASIC has leakage at small nodes). The shape of tradeoffs is similar; the magnitudes differ.

Takeaway: If you design carefully for FPGA (correct synchronous reset, no combinational loops, meet timing comfortably), your RTL is generally ASIC-ready. The RTL discipline you're learning applies both directions.

🤖 Check the Machine

Ask AI: “I have a 16-bit sequential multiplier that runs at 180 MHz on iCE40. If I target Skywater 130 nm ASIC, what rough Fmax should I expect, and what would be different about the design?”

TASK

AI estimates FPGA→ASIC translation.

BEFORE

Predict: ~5× Fmax on ASIC → ~900 MHz. Critical path moves from routing to logic.

AFTER

Strong AI discusses clock tree + leakage. Weak AI just scales numbers linearly.

TAKEAWAY

Cross-target estimates need cost-model awareness, not just scale factors.

Key Takeaways

① Open-source ASIC flow (Yosys + OpenROAD) runs on your laptop.

② Different cost models: FPGA flops are free; ASIC flops are silicon.

③ ASIC Fmax is typically 5× higher than FPGA for the same RTL.

④ Well-designed FPGA RTL is generally ASIC-ready. RTL discipline transfers.

The RTL discipline is universal. The cost models are target-specific.

Pre-Class Self-Check

Q1: On an FPGA, what's the dominant factor in the critical path delay?

Routing (net delay between LUTs). FPGA logic is fast; moving signals around via configurable switches is slow.

Q2: On an ASIC at 130 nm, which is typically a bigger power concern: static leakage or dynamic switching?

Dynamic (at larger nodes like 130 nm). At <28 nm, static leakage starts to dominate. Depends on node and activity.

Pre-Class Self-Check (cont.)

Q3: What open-source ASIC tool handles placement and routing?

OpenROAD. Wrapper automation: OpenLane.

Q4: Your iCE40 design has 100 MHz Fmax. What's a reasonable expectation on Skywater 130 nm, and why?

~400-700 MHz, typical 4-7× increase. ASIC standard cells and routing are faster than FPGA LUT+interconnect. Actual results require a real flow run.

🔗 End of Day 10

Tomorrow: UART — Real Serial Communication

Day 11 · Protocol, Architecture, Implementation, PC Connection

▸ WHY THIS MATTERS NEXT

You now have a complete toolkit: logic, state machines, memory, verification, hierarchy, timing, PPA. Day 11 puts it all together in one ambitious project: a UART transmitter that talks to your laptop. You'll compose your Week 2 modules (piso_shift, mod_n_counter, FSM) into a real communication link. By end of Day 11, your Go Board says “HELLO” to your terminal over a serial cable. This is where FPGAs get fun.