Day 9 · Memory Architecture

iCE40 Memory Resources

Video 3 of 4 · ~8 minutes

Dr. Mike Borowczak · Electrical & Computer Engineering · CECS · UCF

🌍 Where This Lives

In Industry

Every FPGA chip family has a fixed number of memory blocks: iCE40 HX1K has 16 EBRs. iCE40 UP5K has 128 SPRAM + 30 BRAM. Xilinx Artix-7 has 135 BRAM36Ks (~4.8 Mbit). Intel Cyclone V has 3.3 Mbit. When you buy a chip, you buy a fixed memory budget — designs that don't fit are redesigned. Datasheet comprehension is career-critical.

In This Course

Every design from here to capstone must fit within 1280 LUTs + 64 Kbit of block RAM. Today's memory-planning skills are what let you size ambitious projects. Trying to cram a 256-character text frame buffer in without understanding EBRs? You'll fail synthesis. Understanding the budget? You'll allocate 2 EBRs and move on.

⚠️ EBRs Are a Fixed Budget, Not a Lake

❌ Wrong Model

“The FPGA has 64 Kbit of block memory, so I can fit any combination of RAMs up to that total. A 3 Kbit RAM + a 5 Kbit RAM + a 2 Kbit RAM = 10 Kbit, and I've got 54 Kbit left.”

✓ Right Model

Block RAM comes in fixed-size units: 16 blocks × 4 Kbit each. A 3 Kbit RAM consumes 1 whole EBR. A 5 Kbit RAM consumes 2 EBRs (overflows into a second block). A 2 Kbit RAM consumes 1 EBR. Total EBR cost: 1 + 2 + 1 = 4 EBRs, not a “10 Kbit” calculation. Always round up to the next whole block.

The receipt: Planning memory by total bits is a beginner's mistake. Each RAM rounds up. A design with 16 tiny 256-bit RAMs exhausts the chip's EBR count even though total bits = 4 Kbit.

👁️ I Do — The iCE40 HX1K Datasheet

Resource	Count	Per-unit	Total
Logic cells (LUT4 + DFF)	1,280	—	1,280 LUTs
Embedded Block RAM (EBR)	16	4 Kbit	64 Kbit
PLLs	1	—	1
I/O pins	up to 96	—	—
SPI config flash	1	external	8 Mbit typ.

My thinking: 1,280 LUTs is the combinational + sequential budget. 16 EBRs is the memory budget. They're independent — using all your EBRs doesn't reduce LUT availability. This is why block RAM is so valuable: it's free silicon you can't do anything else with.

🤝 We Do — EBR Aspect Ratios

Each 4 Kbit EBR can be configured in 5 different shapes:

Aspect Ratio	Depth × Width	Typical Use
256 × 16	256 words	Coefficient table, char ROM (16-bit ASCII)
512 × 8	512 bytes	UART FIFO, text buffer, 7-seg char ROM
1024 × 4	1024 nibbles	Audio sample table (4-bit PCM)
2048 × 2	2048 dibits	Rare — dense packed data
4096 × 1	4096 bits	Bitmap pixels, BCD encodings

Together: The synthesizer picks the aspect ratio from your Verilog widths. Declare reg [7:0] mem [0:511] → 512×8 aspect. Declare reg [15:0] mem [0:255] → 256×16. If you need more depth or width than one EBR supports, the tool automatically concatenates multiple EBRs.

🧪 You Do — Memory Budget Exercise

A design needs: UART TX FIFO (256 × 8), UART RX FIFO (256 × 8), character ROM for VGA (128 × 64), sine lookup (1024 × 10). How many EBRs?

Answer:

TX FIFO: 256 × 8 = 2 Kbit → 1 EBR (fits in 512×8 mode)
RX FIFO: 256 × 8 = 2 Kbit → 1 EBR
Character ROM: 128 × 64 = 8 Kbit → 4 EBRs (need 64-bit width, so 4 EBRs of 16-bit width combined)
Sine lookup: 1024 × 10 = 10 Kbit → 3 EBRs (1024×10 rounds up to 1024×16 + needs 3 EBRs to provide enough bits)
Total: 9 of 16 EBRs (56%). Fits with 7 EBRs to spare.

🔧 Read the Tool's Verdict

$ yosys -p "read_verilog *.v; synth_ice40 -top top_design; stat" -q
=== top_design ===
   Number of cells:                 480
     SB_CARRY                        45
     SB_DFFE                        120
     SB_LUT4                        280
     SB_RAM40_4K                      9    ← 9 EBRs used
                                            (56% of 16 available)

What to notice: SB_RAM40_4K count matches your budget estimate. If it doesn't — if you expected 3 and got 8 — some RAM wasn't inferred and got scattered. Bug. If it's bigger than 16, your design does not fit on this chip — redesign or re-target.

Next-pnr check: After Yosys, nextpnr-ice40 reports utilization with “Device utilization: LCs 34%, BRAMs 56%”. That's the final authority on whether you fit. Watch those numbers grow through a project.

🤖 Check the Machine

Ask AI: “I'm targeting an iCE40 HX1K (16 × 4Kbit EBRs, 1280 LUTs). Can I fit a 2048-entry × 32-bit lookup table? If not, what do I do?”

TASK

AI does a resource-fit analysis.

BEFORE

Predict: 2048 × 32 = 64 Kbit. Exactly the full EBR budget. Any other memory = doesn't fit.

AFTER

Strong AI: “Fills all EBRs, leaves no other memory. Consider halving precision or storing half-ROM with symmetry.”

TAKEAWAY

Architecture-aware problem solving is a hallmark of senior AI help.

Key Takeaways

① iCE40 HX1K: 1280 LUTs + 16 EBRs × 4 Kbit = 64 Kbit block RAM.

② EBRs are fixed units. Always round up when budgeting.

③ Aspect ratios: 256×16, 512×8, 1024×4, 2048×2, 4096×1. Tool picks automatically.

④ Budget before coding. Verify with make stat.

Every EBR you leave unused is free silicon thrown away.

🔗 Transfer

Practical Memory Applications

Video 4 of 4 · ~8 minutes

▸ WHY THIS MATTERS NEXT

Pattern + budget = what can you build? Video 4 puts it together with a concrete application: a pattern sequencer that uses ROM + a counter to produce arbitrary LED animations, sine waves, or character displays. You'll see how the memory resources from today become real-world behavior.