Day 4 · Sequential Logic Fundamentals

Clocks & Edges

Video 1 of 4 · ~12 minutes

Dr. Mike Borowczak · Electrical & Computer Engineering · CECS · UCF

🌍 Where This Lives

In Industry

Every digital chip built since 1970 runs on clocks. Your phone's SoC has 50+ clock domains running at frequencies from 32 kHz to 3 GHz. Clock distribution is a whole specialty — PLLs, clock trees, skew analysis. Today is your first formal introduction to the concept that governs all modern digital design: Register Transfer Level.

In This Course

Every sequential lab from here uses a clock. Day 4 counter. Day 5 debouncer. Day 6 testbench stimulus. Day 7 FSM. Day 11 UART. Day 14 assertions. Get the clock mental model right today and everything downstream falls into place.

Career tag: “Synchronous design” isn't one methodology among many — it's the methodology. Everything you'll build in school or at a company is synchronous. Asynchronous design exists but is specialized (resets, clock-domain crossings, GALS systems).

⚠️ The Clock Doesn't Drive Your Code

❌ Wrong Model

“The clock is like a loop counter. Every time the clock ticks, the always @(posedge clk) block runs once, statement by statement.”

✓ Right Model

The clock is a capture signal. On each rising edge, every flip-flop simultaneously snapshots its D input. Between edges, combinational logic churns continuously — settling on what will become the next D values. The code describes the structure; the clock just says “snapshot now.”

The receipt: A 100-line always @(posedge clk) block doesn't take 100× longer to “run” than a 1-line one. All flops capture in parallel. The length of the block affects routing and area, not time.

The Clock: Heartbeat of Sequential Logic

         ┌───┐   ┌───┐   ┌───┐   ┌───┐
clk  ────┘   └───┘   └───┘   └───┘   └───
         ↑       ↑       ↑       ↑
     posedge  posedge  posedge  posedge

On each positive edge, every flip-flop captures its input. Between edges, combinational logic computes next values.

This is Register Transfer Level (RTL) — the fundamental abstraction of synchronous design.

The Go Board's Clock

Frequency: 25 MHz crystal oscillator (pin 15)

Period: 1 / 25,000,000 = 40 ns

Problem: 25 MHz is far too fast for human eyes (persistence of vision kicks in around 24-60 Hz).

Solution: Clock divider — your first real sequential design!

To blink an LED at 1 Hz, count 25,000,000 clock cycles between toggles. That requires a flip-flop — which requires always @(posedge clk).

👁️ I Do — The Fundamental Sequential Pattern

always @(posedge i_clk) begin
    r_q <= r_d;    // D flip-flop: capture on rising edge
end

What it does

On every rising edge, r_q captures r_d. Between edges, r_q holds.

What it creates

A D flip-flop — the 1-bit memory element of synchronous design. On iCE40: an SB_DFF primitive.

My thinking: Three mandatory elements: posedge clk in the sensitivity list, reg-declared LHS, <= for the assignment. Miss any of the three and you've written something that isn't a synchronous flip-flop.

🤝 We Do — What's Missing?

// Three attempts at a D flip-flop. Which work?
// Attempt 1:
always @(posedge clk) q = d;

// Attempt 2:
always @(clk) q <= d;

// Attempt 3:
always @(*) q <= d;

Answers: (1) Works mechanically but uses blocking = — OK for a single register, but catastrophic if the block grows. Don't write this. (2) Triggers on any transition of clk (both edges) — synthesis warns, behavior unpredictable. Wrong. (3) Combinational sensitivity with nonblocking — pointless and produces a latch. Very wrong.

🧪 You Do — Predict the Waveform

Given d toggles at 10 MHz and clk is 25 MHz, sketch q:

clk ─┐_┌─┐_┌─┐_┌─┐_┌─┐_┌─┐_┌─┐_┌─
d   ──────┐___________┌─────────
q   ?

Answer: q updates on each posedge clk, capturing whatever d was a few picoseconds before the edge. Since d isn't synchronized to clk, q may sample either high or low depending on exact alignment. This is a metastability hazard — covered in detail on Day 5.

Lesson: A clocked register only updates on the clock's edge, but the value it captures depends on whether the input was stable at that moment. Sampling an asynchronous input is dangerous — Day 5 shows the synchronizer pattern that fixes it.

▶ LIVE DEMO

One-Flop, Two-Flop in GTKWave

~4 minutes

▸ COMMANDS

cd labs/week1_day04/ex1_dff/
make sim       # iverilog testbench
make wave      # GTKWave
make stat      # yosys synth_ice40

▸ EXPECTED STDOUT

PASS: d=1 → q=1 after edge
PASS: d=0 → q=0 after edge
PASS: q stays through many
  cycles when d stable
=== 8 passed, 0 failed ===

▸ GTKWAVE

Add clk · d · q. Look for: q transitions happen right after each posedge of clk, never between edges. The step-function shape is the visual signature of synchronous design.

🔧 What Did the Tool Build?

$ yosys -p "read_verilog dff.v; synth_ice40 -top dff; stat" -q

=== dff ===
   Number of wires:                  4
   Number of cells:                  1
     SB_DFF                          1    ← one flip-flop, finally!
     SB_LUT4                         0

First flop of the course. Until today, every module synthesized to 0 SB_DFFs. Now we have one. This is the first hardware primitive that remembers — the building block of every sequential design you'll write.

iCE40 primitive: SB_DFF is a positive-edge-triggered D flip-flop with synchronous set/reset capability. There are ~1200 of them on the HX1K. That's your “state budget” for any design.

🤖 Check the Machine

Ask AI: “In Verilog, why does always @(posedge clk) q <= d; create a flip-flop, but always @(*) q <= d; does not?”

TASK

Ask AI: why the sensitivity list determines the storage.

BEFORE

Predict: posedge = edge-triggered storage = flop. @(*) = level-sensitive = combinational or latch.

AFTER

Strong AI mentions edge-trigger semantics explicitly. Weak AI says “because of the clock” without explaining why.

TAKEAWAY

The sensitivity list is structural: it describes the kind of hardware to build.

Key Takeaways

① Clock edges define when state changes — always @(posedge clk).

② Between edges, combinational logic computes next values.

③ Go Board: 25 MHz. To make visible events, divide the clock.

④ This is RTL — the design abstraction used everywhere.

Between edges: combinational settles. On the edge: flops capture. Repeat forever.

🔗 Transfer

Nonblocking Assignment

Video 2 of 4 · ~12 minutes

▸ WHY THIS MATTERS NEXT

You used <= in the D-flop example without really understanding why. Video 2 makes it rigorous with a side-by-side waveform demo: same shift-register code, one with = and one with <=, and you'll see the blocking version collapse.